The present invention relates to a frequency multiplier circuit used in semiconductor integrated circuits, and in particular to a frequency multiplier circuit used for a microcomputer requiring a clock signal having a frequency in the range of several MHz to several tens MHz.
Heretofore, a frequency multiplied signal of a clock signal supplied from the outside is generated by using a phase-locked loop (hereafter referred to as PLL) circuit. FIG. 9 shows an example of a conventional frequency multiplier circuit using a voltage controlled oscillator circuit.
As shown in FIG. 9, a voltage controlled oscillator circuit (VCO) 11 is, for example, a ring oscillator formed of a large number of stages of inverter circuits 12 connected in series. In other words, an output terminal of an inverter circuit of located at a final stage is connected to an input terminal of an inverter circuit located at a first stage. Each inverter circuit 12 is formed of an inverter 15, and control transistors 13 and 14 respectively supplied with control voltages VP and VN at respective gates. The delay value of the inverter circuit 12 is controlled by the control voltages VP and VN. As a result, the oscillation frequency of the voltage controlled oscillator circuit 11 is controlled. An oscillation signal CKOUT of the voltage controlled oscillator circuit 11 is output to the outside as a frequency multiplied clock signal, and supplied to an input terminal of a frequency divider circuit 16. The frequency divider circuit 16 divides the frequency of the oscillation signal CKOUT of the voltage controlled oscillator circuit 11 to 1/N, and outputs a resultant frequency divided signal. A first input terminal of a phase comparator (PC) 17 is supplied with the frequency divided signal. A second input terminal of the phase comparator 17 is supplied with an external reference clock signal CKIN. The phase comparator 17 detects a lead or lag of the phase between the frequency divided signal and the external reference clock signal, converts a result thereof to a pulse signal, and outputs the pulse signal as an error signal. The error signal is supplied to an input terminal of a low-pass filter (LPF) 18. The low-pass filter 18 outputs only the direct current component of the error signal. The output signal of the low-pass filter 18 is used as the control voltage VN of the voltage controlled oscillator circuit 11.
Furthermore, an output terminal of the low-pass filter 18 is connected to a gate of an N-channel MOS transistor 19. A source of the N-channel MOS transistor 19 is grounded. A drain of the N-channel MOS transistor 19 is connected to a drain and a gate of a P-channel MOS transistor 20. A source of the P-channel MOS transistor 20 is supplied with a power supply voltage. A drain potential of the N-channel MOS transistor 19 is used as the control voltage VP of the voltage controlled oscillator circuit 11. In this way, the control voltage VP is determined by using the control voltage VN.
In the circuit shown in FIG. 9, negative feedback control is conducted on the VCO 11 in such a direction as to make the external reference clock signal CKIN coincide with the output signal of the frequency divider circuit 16 in frequency and phase. As a result, the frequency multiplied clock signal CKOUT becomes an N frequency multiplied signal of the external reference clock signal CKIN.
FIG. 11 shows a circuit example of a frequency multiplier circuit using a voltage controlled delay circuit. As shown in FIG. 11, the external reference clock signal CKIN is supplied to an input terminal of a voltage controlled delay circuit 21. The voltage controlled delay circuit 21 is formed of a large number of inverter delay cell stages connected in series. A first terminal and a second terminal of the phase comparator (PC) 22 are supplied with an output signal of an inverter delay cell forming the final stage of the voltage controlled delay circuit 21 and the external reference clock signal CKIN, respectively. An output terminal of the phase comparator 22 is connected to an input terminal of the low-pass filter 23. An output terminal of the low-pass filter 23 is connected to a control voltage input terminal of the voltage controlled delay circuit 21. By this negative feedback loop, delay values of respective inverter delay cells of the voltage controlled delay circuit 21 are adjusted so as to make the output signal of the inverter delay cell forming the final stage of the voltage controlled delay circuit 21 coincide with the external reference clock signal CKIN in frequency and phase.
A logic circuit 24 has a plurality of input terminals. Those input terminals are connected to suitably selected output terminals of inverter delay cells forming the voltage controlled delay circuit 21. The logic circuit 24 outputs a plurality of pulse signals every period of the external reference clock signal CKIN. By suitably forming an internal circuit of the logic circuit 24, an output signal CKOUT of the logic circuit 24 can be made a clock signal frequency multiplied with respect to the reference clock signal CKIN.
When the PLL circuit has arrived at its stable state, therefore, the logic circuit 24 outputs the clock signal frequency multiplied with respect to the external reference clock signal.
In the PLL circuit shown in FIG. 9, the oscillation signal CKOUT of the voltage controlled oscillator circuit 11 has an oscillation frequency fVCO represented by the relation EQU fVCO=N.times.fIN
where fIN is the frequency of the external reference clock signal CKIN, and N is the frequency division factor of the frequency divider circuit 16. For example, if fIN is in the range of 1 MHz to 4 MHz, and N is in the range of 2 to 8, then fVCO needs to be in the range of 2 MHz to 32 MHz. In this way, the voltage controlled oscillator circuit is required to oscillate in a very wide range of frequency.
FIG. 10 shows a relation between the oscillation frequency of the voltage controlled oscillator circuit and the control voltage VN of the voltage controlled oscillator circuit.
As represented by a region 31 shown in FIG. 10, the oscillation frequency of the voltage controlled oscillator circuit saturates as the control voltage of the voltage controlled oscillator circuit becomes high. Therefore, a fixed upper limit exists in the control voltage. Furthermore, since the control voltage VN is applied to the gate terminal of the N-channel MOS transistor 19 as shown in FIG. 9, the voltage controlled oscillator circuit does not oscillate when the control voltage VN is lower than the threshold voltage of the N-channel MOS transistor 19. Therefore, a lower limit of the control voltage also exists. In this way, the control voltage range of the voltage controlled oscillator circuit becomes narrow.
On the other hand, it is necessary to conduct the design so as to provide the maximum oscillation frequency of the voltage controlled oscillator circuit with a considerably high value, considering the process dispersion and the power supply voltage range or the temperature range.
Typically in a narrow range of the control voltage, therefore, a wide range of the oscillation frequency is controlled. As represented by a region 32 of FIG. 10, therefore, the oscillation characteristic of the voltage controlled oscillator circuit becomes very steep.
For example, in the case where this voltage controlled oscillator circuit is incorporated in a MCU and noise is mixed in the control voltage, the oscillation frequency is significantly changed by the noise because the oscillation characteristic is steep. This results in a problem that it becomes impossible to obtain the stable frequency multiplied clock output.
If the frequency of the external reference clock signal CKIN changes in a wide range in the example of the conventional frequency multiplier circuit using the multi-stage voltage controlled delay circuit shown in FIG. 11, the delay value per inverter delay cell stage must be adjusted in a wide range. FIG. 12 shows the relation between the control voltage VN and the delay value in each inverter delay cell. In the inverter delay cell, a delay value smaller than a fixed value cannot be obtained as represented by a region 35. Furthermore, if the delay value becomes large, a change of the delay value with respect to a change of the control voltage becomes very large as in the region 33. If noise is mixed in the control voltage, therefore, the delay value of the delay circuit changes largely. This results in a drawback that a stable frequency multiplied clock signal is not output.
A change of the frequency or pulse width caused in the frequency multiplied clock signal by noise as described above is called jitter. A change of the phase caused in the frequency multiplied clock signal is called phase error. The performance of the frequency multiplier circuit largely depends upon whether the jitter and phase error is large or small. For example, in the case where a frequency multiplier circuit is used in a microcomputer, jitter or a phase error causes false operation or runaway. Furthermore, in the case where the frequency multiplier circuit is applied to liquid crystal TV sets and the frequency multiplied clock signal is used as a clock signal for sampling a video signal every horizontal pixel, flicker, fluctuation, or the like of the picture is caused.
In the conventional frequency multiplier circuit, a voltage controlled oscillator circuit having a wide frequency range allowing oscillation or inverter delay cells having a delay value which can be controlled in a wide range are needed. This results in a problem that the sensitivity of the frequency multiplied clock signal with respect to the noise is increased.